INFOZOIC, Inc.‘s Design Verification (DV) Links Page
About Infozoic FAQ What are all these silly Acronyms?
1. ?
2. EDAC
General and Newswww.janick.bergeron.com/guild/ Verification Guild (he da man!)
www.deepchip.com Industry News
www.hdlcon.org Design and Verification Conference
http://www.cadence.com/articles/inca.html “Siliconization” and the Interleaved Native Compiled-Code Architecture
Tools Vendorswww.axiscorp.com
www.Cadence.com Quickturn division
www.Mentor.com Ikos + Meta Systems => Mentor Emulation Division (MED)
www.Synopsys.com Co-Design Automation Inc.
www.RealIntent.com (“Verix”, DAS)
http://www.eedesign.com/story/OEG20020304S0018 Tools
model / ISA / bfm
/ ffm http://www.ics.uci.edu/~rgupta/cores/dac97/gif/part4/sld040.htm
http://www.chipcenter.com/asic/products_200-299/prod262.html
summary of HDL approaches
HDL Simulators
Cadence NC-SIM
Modeltech VSIM
Other tools (viewers, timingdesigner, analysis, …)
Synopsys Vera HVL Co-design Automation: SuperLog
Verisity Specman E
Cadence Testbuilder and VRM http://www.cadence.com/company/OpenSystemC.html
Forte Systems Cynlib => ESC migrated to systemC?V?
Co-verification
(HW / SW)
“Joint
verification” -- hardware, software, algorithms
and architectures; transaction-level modeling
Debugging embedded buses,
etc. http://www.esconline.com/sf/program_descr.htm#441
Coverage Tools
Synopsys/Co-Design Design Assertion Subset (DAS) => OpenVera OVA www.open-vera.com
www.0-in.com Checkerware, 0-In Search
Static Timing Analysis (STA)
MOTIVE
PrimeTime
Pearl
Equivalence checkers:
Formal and Semi-Formal
Property Checking
Synopsys FormalVera
Next-generation integrated languages (synthesis, verification, assertions, formal methods, abstraction)
systemC www.systemc.org Open systemC Initiative
Cadence systemC verification library (SCV)
systemVerilog www.accellera.org (from Open Verilog International [OVI] and VHDL International)
Accellera Accellera standards organization (OVI + VHDL Int’l)
http://www.dacafe.com/DACafe/Review/20020624.html
Verilog extension
adds behavioral design
Successor to Verilog approved as Accellera standard
http://www.chipcenter.com/asic/products_200-299/prod277.html
http://www.siliconstrategies.com/story/OEG20020610S0044 wrt Sugar/PSL
http://www.insurancetech.com/story/update/OEG20020801S0047
dirt: http://www.eedesign.com/story/OEG20020226S0041
Other
Rosetta Blooms for System-level Design SystemC + SystemVerilog + Rosetta
www.UML.org Unified
Modeling Language
Cadence Assura™ Verification
Ver. 2.0
New signal integrity challenges process variations/yield issues
Antenna rules, dummy metal fill rules, metal slotting rules,
constraints on stacked vias, and layout rules for optical proximity correction
and phase-shift masks
Technology aware STA
BIST and structural test
Specific Verification Challenges
Challenges in
HyperTransport Verification
Books
Research
Glossary click here
Intellectual
Property click
here
HDL
Information click here
SOC Information click here
ASIC Information click here
FPGA
Information click here
Verification Information click here